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DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation rev. 03 ? 2 july 2012 product data sheet 1. general description the DAC1003D160 is optimized to reduce architecture complexity and overall system cost. the digital-to-analog converter (dac) lea ds dynamic performance in multi-carrier support because of its direct if conversion capabilities. with an internal sampling rate up to 160 mhz, the DAC1003D160 is an extr emely competitive solution for broadband wireless systems transmitters, as well as a wide range of applications. 2. features ? dual 10-bit resolution ? s purious free dynamic range (sfdr) = 80 dbc at 2.5 mhz ? input dat a rate up to 80 mhz ? 2 ? interpolation filter ? output dat a rate up to 160 mhz ? sing le 3.3 v power supply ? l ow noise capacitor free integrated phase-locked loop (pll) ? low power diss ipation ? htqf p80 package ? am bient temperature from ? 40 ? c to + 85 ? c 3. applications ? broadband wireless systems ? digit al radio links ? cellular base stations ? instru mentation ? ca ble modems ? ca ble modem termination system (cmts) /data over cable service interface specification (docsis)
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 2 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 4. ordering information table 1. ordering information type number package name description version DAC1003D160hw htqfp80 plastic thermal enhanced thin quad flat package; 80 leads; bod y 12 ? 12 ? 1 mm; exposed die pad sot841-1 5. block diagram 10 10 014aaa532 pll DAC1003D160 fir fir 10 10 10 (clk 2) (clk 2) (clk 2) clock driver latch latch 10 5 clk 2, 8 i.c. 10, 51 v ccd (1) v cca (2) agnd (3) dgnd (4) dec 6 31 to 34, 37 to 42 11 to 16, 19 to 22 dac dac internal band gap clkn q9 to q0 i9 to i0 ioutn gapout 69 73 68 72 iout qout qoutn 58 57 gapd 60 ivires u/i v cca v cca u/i 59 qvires (1) pins 1, 3, 61, 65, 76 and 80. (2) pins 4, 7, 62, 64, 66, 67, 70, 71, 74, 75, 77 and 79. (3) pins 9, 17, 25, 29, 30, 35, 44, 49, 50, 52, 53, 54, 55 and 56. (4) pins 18, 26, 36, 43, 63 and 78. fig 1. block diagram
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 3 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 6. pinning information 6.1 pinning DAC1003D160 v cca ivires i.c. qvires v cca gapout agnd gapd clk dgnd clkn dgnd agnd dgnd i.c. dgnd dgnd dgnd v ccd v ccd i9 dgnd i8 dgnd i7 n.c. i6 n.c. i5 n.c. i4 n.c. dgnd dgnd dec dec i3 q0 i2 q1 i1 v cca i0 agnd n.c. dec n.c. agnd dgnd v cca dec agnd n.c. agnd n.c. iout dgnd ioutn dgnd agnd q9 agnd q8 qout q7 qoutn q6 agnd dgnd agnd dec v cca q5 agnd q4 dec q3 agnd q2 v cca 014aaa533 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 dgnd fig 2. pin configuration 6.2 pin description table 2. pin description symbol pin type [1] description v cca 1 s analog supply voltage i.c. 2 i/o internally connected; leave open v cca 3 s analog supply voltage agnd 4 g analog ground clk 5 i clock input clkn 6 i complementary clock input agnd 7 g analog ground i.c. 8 o internally connected; leave open dgnd 9 g digital ground
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 4 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation v ccd 10 s digital supply voltage i9 11 i i data input bit 9 (most significant bit (msb)) i8 12 i i data input bit 8 i7 13 i i data input bit 7 i6 14 i i data input bit 6 i5 15 i i data input bit 5 i4 16 i i data input bit 4 dgnd 17 g digital ground dec 18 o decoupling node i3 19 i i data input bit 3 i2 20 i i data input bit 2 i1 21 i i data input bit 1 i0 22 i i data input bit 0 (least significant bit (lsb)) n.c. 23 i not connected n.c. 23 i not connected dgnd 25 g digital ground dec 26 o decoupling node n.c. 27 i not connected n.c. 28 i not connected dgnd 29 g digital ground dgnd 30 g digital ground q9 31 i q data input bit 9 (msb) q8 32 i q data input bit 8 q7 33 i q data input bit 7 q6 34 i q data input bit 6 dgnd 35 g digital ground dec 36 o decoupling node q5 37 i q data input bit 5 q4 38 i q data input bit 4 q3 39 i q data input bit 3 q2 40 i q data input bit 2 q1 41 i q data input bit 1 q0 42 i q data input bit 0 (lsb) dec 43 o decoupling node dgnd 44 g digital ground n.c. 45 i not connected n.c. 46 i not connected n.c. 47 i not connected n.c. 48 i not connected dgnd 49 g digital ground dgnd 50 g digital ground table 2. pin description ?continued symbol pin type [1] description
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 5 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation [1] type description: s: supply; g: ground; i: input; o: output. v ccd 51 s digital supply voltage dgnd 52 g digital ground dgnd 53 g digital ground dgnd 54 g digital ground dgnd 55 g digital ground dgnd 56 g digital ground gapd 57 i internal band gap power disable input gapout 58 i/o band gap output voltage qvires 59 i q dac biasing resistor ivires 60 i i dac biasing resistor v cca 61 s analog supply voltage agnd 62 g analog ground dec 63 o decoupling node agnd 64 g analog ground v cca 65 s analog supply voltage agnd 66 g analog ground agnd 67 g analog ground qoutn 68 o complementary q dac output current qout 69 o q dac output current agnd 70 g analog ground agnd 71 g analog ground ioutn 72 o complementary i dac output current iout 73 o i dac output current agnd 74 g analog ground agnd 75 g analog ground v cca 76 s analog supply voltage agnd 77 g analog ground dec 78 o decoupling node agnd 79 g analog ground v cca 80 s analog supply voltage table 2. pin description ?continued symbol pin type [1] description
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 6 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 7. functional description the DAC1003D160 is a segmented architecture composed of a 7-bit thermometer sub-dac and the remaining 3-bit in a binary weighted sub-dac. the device produces two complementary current ou tputs on both channels, respectively pins iout/ioutn and qout/qoutn which need to be connected via a load resistor to the ground. figure 3 shows the equivalent analog output circ uit of one d ac, which consists of a parallel combination of pmos current sources and associated switches for each segment. the cascade source configuration enables the increase of the output impedance of the sou rce and the improvement of the dynamic pe rformance of the dac by introducing less distortion. figure 4 shows the internal reference configuration. i n this case the bi as current is given by the output of the internal regulator conn ected to the inverting input of the internal operational amplifiers, while external resistors r i and r q are connected respectively to pins ivires and qvires. thus the output curr ent of the two dacs is typically fixed to 20 ma with an appropriate choice of these resi stor s. this configur ation is optimal for temperature drift compensation because the band gap can be matched with the voltage on the feedback resistors. the relation between full-scale output current i o(fs) and the r i (r q ) is: r i 2048 v gapout ? 82 i ofs ?? ? ----------------------------------------- ? = the output current can also be adjusted by im posing an external reference voltage to the inverting input pin gapout and disabling the internal band gap with pin gapd set to high. at a voltage lower than 1.2 v the current can be set at values lower than 20 ma. th e input references at pins ivires and qvires may also be driven by separate reference voltages to adjust independently the two dac currents. 014aaa537 agnd r l r l agnd iout/qout ioutn/qoutn DAC1003D160 014aaa538 qvires ivires gapout agnd gapd internal band gap i dac current sources array DAC1003D160 q dac current sources array r i r q fig 3. equivalent analog output circuit fig 4. internal reference configuration
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 7 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 8. limiting values table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ccd digital supply voltage [1] ? 0.3 +3.9 v v cca analog supply voltage [1] ? 0.3 +3.9 v ? v cc supply voltage difference between the a nalog and digital supply voltages ? 15 0 +150 mv v i input voltage pins qn and in refere nced to dgnd ? 0.3 v ccd + 0.3 v pins ivires, qvi res, gapd, clk and clkn referenced to agnd ? 0.3 v cca + 0.3 v v o output voltage pins iout, iou tn, qout and qoutn referenced to dagnd ? 0.3 v cca + 0.3 v t stg storage temperature ? 55 +150 ?c t amb ambient temperature ? 40 +85 ?c t j junction temperature - 125 ?c [1] all supplies are connected together. 9. thermal characteristics table 4. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air 27.1 k/w r th(c-a) thermal resistance from case to ambient in free air 11.8 k/w 10. characteristics table 5. characteristics v ccd = v cca = 3.0 v to 3.6 v; agnd and dgnd connected together; t amb = ? 40 ? c to +85 ? c; typical values measured at v ccd = v cca = 3.3 v, i o(fs) = 20 ma and t amb = 25 ? c; dynamic parameters measured using output schematic given in figure 10; unless otherwise specified. symbol parameter conditions min typ max unit supplies v ccd digital supply voltage 3.0 3.3 3.6 v v cca analog supply voltage 3.0 3.3 3.6 v i ccd digital supply current - 55 65 ma
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 8 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation i cca analog supply current - 73 85 ma p tot total power dissipation f clk = 80 mhz; f iout = f qout = 5 mhz - 422 540 mw clock inputs (clk and clkn) v i(cm) common-mode input voltage - 1.65 - v v i(dif)(p-p) peak-to-peak differential input voltage - 1.0 - v analog outputs (iout, ioutn, qout and qoutn) i o(fs) full-scale output current differential outputs 4 - 20 ma r o output resistance [1] - 150 - k : c o output capacitance [1] - 3 - pf digital inputs (i0 to i9, q0 to q9 and gapd) v il low-level input voltage dgnd - 0.3 v ccd v v ih high-level input voltage 0.7 v ccd - v ccd v i il low-level input current v il = 0.3 v ccd - 5 - p a i ih high-level input current v ih = 0.7 v ccd - 5 - p a reference voltage output (gapout) v gapout voltage on pin gapout - 1.31 - v i gapout current on pin gapout external voltage - 1 - p a ' v gapout voltage variation on pin gapout - r 133 - ppm/ q c clock timing inputs (clk and clkn) f clk clock frequency - 80 mhz t w(clk)h high clock pulse width 5 - - ns t w(clk)l low clock pulse width 5 - - ns input timing (i0 to i9 an d q0 to q9); see figure 5 t h(i) input hold time 1.1 - 3.4 ns t su(i) input set-up time 1.5 - +0.7 ns output timing (iout, ioutn, qout, qoutn) t s settling time t o r 0.5 lsb [1] - 16 - ns digital filter specification (fir); order n = 42 see figure 6 and 7 and table 7 f data data rate - - 80 mhz d ripple(pb) pass-band ripple f data /f clk ; 0.005 db attenuation - 0.405 - b p power bandwidth f data /f clk ; 3 db attenuation - 0.479 - d stpb stop-band attenuation f data /f clk = 0.6 db to 1 db - 69 - db t d(grp) group delay time - 11 t clk - ns analog signal processing inl integral non-linearity - r 0.2 - lsb dnl differential non-linearity - r 0.1 - lsb table 5. characteristics ?continued v ccd = v cca = 3.0 v to 3.6 v; agnd and dgnd connected together; t amb = 40 q c to +85 q c; typical values measured at v ccd = v cca = 3.3 v, i o(fs) = 20 ma and t amb = 25 q c; dynamic parameters measured using output schematic given in figure 10; unless otherwise specified. symbol parameter conditions min typ max unit
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 9 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation [1] guaranteed by design. table 6. band gap band gap disable (gapd) band gap input/output (gapout) internal band gap low output (v gapout = 1.2 v) enable high input disable i n(o) output noise current - 120 - pa/ ? hz e offset offset error relative to full-scale - ? 0. 3 - % e g gain error relative to full-scale ? 5.4 - +5.4 % ? g iq iq gain mismatch between i and q, relative to full-scale - ? 0. 2 - % sfdr spurious free dynamic range f clk = 80 mhz; b = nyquist f o = 2.5 mhz at 0 dbfs - 80 - dbc f o = 5 mhz at 0 dbfs - 72 - dbc f o = 13 mhz at 0 dbfs - 64 - dbc ? 2h second harmonic level f o = 5 mhz - 73 - dbc f o = 13 mhz - 65 - dbc ? 3h third harmonic level f o = 5 mhz - 88 - dbc f o = 13 mhz - 86 - dbc imd2 second-order i ntermodulation distortion f clk = 80 mhz; f o 1 = 10 mhz; f o 2 = 12 mhz; b = nyquist - 65 - dbc imd3 third-order intermodulation di stortion f clk = 80 mhz; f o 1 = 10 mhz; f o 2 = 12 mhz - 84 - dbc thd total harmonic distortion f clk = 80 mhz; b = nyquist; t amb = 25 ?c f o = 2.5 mhz - 75 - dbc f o = 5 mhz 68 71 - dbc nsd noise spectral density f clk = 80 mhz f o = 2.5 mhz - ? 15 5 - dbm/hz f o = 5 mhz - ? 15 5 - dbm/hz f o = 19 mhz - ? 15 3 - dbm/hz s/n signal-to-noise ratio f clk = 80 msample/s; b = nyquist f o = 2.5 mhz - 80 - dbc f o = 5 mhz 70 80 - dbc f o = 19 mhz - 78 - dbc acpr adjacent channel power ratio baseband; 5 mhz channel spacing; b = 3.84 mhz f o = 2.5 mhz - 60 - dbc f o = 20 mhz - 61 - dbc table 5. characteristics ?continued v ccd = v cca = 3.0 v to 3.6 v; agnd and dgnd connected together; t amb = ? 40 ? c to +85 ? c; typical values measured at v ccd = v cca = 3.3 v, i o(fs) = 20 ma and t amb = 25 ? c; dynamic parameters measured using output schematic given in figure 10; unless otherwise specified. symbol parameter conditions min typ max unit
014aaa534 q0 to q9 t su(i) t h(i) clkn clk iout/ioutn, qout/qoutn 50 % i0 to i9, fig 5. input timing diagram DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 10 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 11 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation normalized frequency f o/ f clk 0 1.0 0.8 0.4 0.6 0.2 014aaa535 ?100 ?60 ?140 ?20 20 output (db) ?180 t (sample) 040 30 10 20 014aaa536 0.2 0 0.4 0.6 normalized output ?0.2 fig 6. fir filter frequency response fig 7. fir filter impulse response table 7. interpolation fir filter coefficient coefficient coefficient value h(1) h(43) 10 h(2) h(42) 0 h(3) h(41) ? 31 h(4) h(40) 0 h(5) h(39) 69 h(6) h(38) 0 h(7) h(37) ? 13 8 h(8) h(36) 0 h(9) h(35) 248 h(10) h(34) 0 h(11) h(33) ? 41 9 h(12) h(32) 0 h(13) h(31) 678 h(14) h(30) 0 h(15) h(29) ? 1 083 h(16) h(28) 0 h(17) h(27) 1 776 h(18) h(26) 0 h(19) h(25) ? 3 282 h(20) h(24) 0 h(21) h(23) 10 364 h(22) - 16 384
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 12 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 11. application information 014aaa539 1 k 100 nf v th 1 k agnd clkn v cca clk DAC1003D160 r s 014aaa540 1 k 100 nf 1 k clkn v cca agnd agnd agnd clk DAC1003D160 1 k 1 k 100 nf 100 nf fig 8. single-ended clock schematic fig 9. differential clock schematic
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 13 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation c DAC1003D160 v cca ivires i.c. qvires v cca gapout agnd gapd clk dgnd clkn dgnd agnd dgnd agnd 3.3 v agnd 3.3 v agnd dgnd 3.3 v dgnd dgnd dgnd dgnd dgnd 3.3 v dgnd dgnd i.c. dgnd dgnd dgnd v ccd v ccd i9 dgnd i8 dgnd i7 n.c. i6 n.c. i5 n.c. i4 n.c. dgnd dgnd dec dec i3 q0 i2 q1 i1 v cca i0 agnd n.c. dec n.c. agnd dgnd v cca dec agnd n.c. agnd n.c. iout dgnd ioutn dgnd agnd q9 agnd q8 qout q7 qoutn q6 agnd dgnd dec agnd v cca q5 agnd q4 dec q3 agnd q2 v cca 014aaa541 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 c c c c c 1.5 k 1.5 k c c c agnd agnd agnd agnd agnd agnd agnd 3.3 v 3.3 v 3.3 v 3.3 v c c cc cc c 50 50 (rload) 50 agnd agnd c 50 50 (rload) 50 agnd agnd agnd agnd 1:1 1:1 all resistors are 1 % precision resistors. c = 100 nf. fig 10. application diagram
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 14 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 11.1 alternative parts the following alternative parts are also available: table 8. alternative parts type number description sampling frequency dac1403d160 dual 14 bits dac, wi th 2 ? interpolating [1] 160 mhz dac1203d160 dual 12 bits dac, wi th 2 ? interpolating [1] 160 mhz [1] pin to pin compatible
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 15 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 12. package outline references outline version european projection issue date iec jedec jeita sot841-1 ms-026 sot841-1 04-01-15 note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included unit a max mm 1.2 0.15 0.05 1.05 0.95 0.27 0.17 0.20 0.09 12.1 11.9 12.1 11.9 14.15 13.85 14.15 13.85 0.75 0.45 1.45 1.05 1.45 1.05 a 1 dimensions (mm are the original dimensions) htqfp80: plastic thermal enhanced thin quad flat package; 80 leads; body 12 x 12 x 1 mm; exposed die pad 80 21 61 40 12 0 60 41 b p b p d h d eh e b a d h e h y z d z e e e w m w m pin 1 index vb m va m c exposed die pad x a l p detail x l (a 3 ) a 2 a 1 0 5 10 mm scale a 2 a 3 0.25 b p c d (1) e (1) e 0.5 h d 6.05 5.95 d h 6.05 5.95 e h h e l 1 l p v 0.2 w 0.08 y 0.1 z d (1) z e (1) 7 0 fig 11. package outline sot841-1 (htqfp80)
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 16 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 13. abbreviations table 9. abbreviations acronym description fir finite impulse response if intermediate frequency lsb least significant bit msb most significant bit pll phase-locked loop pmos positive-metal oxide semiconductor 14. glossary 14.1 static parameters dnl ? differential non-linearity. the difference between the ideal and the measured ou tput value between successive dac codes. inl ? integral non-linearity. the deviation of the tr ansfer function from a best-fit straight line (linear regression computation). 14.2 dynamic parameters imd2 ? second-order intermodulation distortion. from a dual-tone digital input sine wave ( these two frequencies are close together), the intermodulation distortion product imd2 is the ratio of the rms value of either tone and the rms value of the worst 2nd-order intermodulation product. imd3 ? third-order intermodulation distortion. from a dual-tone digital input sine wave ( these two frequencies are close together), the intermodulation distortion product imd3 is the ratio of the rms value of either tone and the rms value of the worst 3rd-order intermodulation product. sfdr ? spurious free dynamic range. the ratio be tween the rms value of the reconstructed output sine wave and the rms value of the largest spurious observed (harmonic and non-harmonic, excluding dc component) in the frequency domain. s/n ? signal-to-noise ratio. the ratio of the rm s va lue of the reconstructed output sine wave to the rms value of the noise excl uding the harmonics and the dc component. thd ? total harmonic distortion. the ratio of the rms value of the harmonics of the o utput frequency to the rms value of the ou tput sine wave. usually, the calculation of thd is done on the first 5 harmonics.
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 17 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 15. revision history table 10. revision history document id release date data sheet status change notice supersedes DAC1003D160_3 20120702 product data sheet - DAC1003D160_2 DAC1003D160_2 20080813 product data sheet - DAC1003D160_1 modifications: added condition to t ? s in table 5. correction to figure ? 10. DAC1003D160_1 20080612 product data sheet - - 16. contact information for more information or sales office addresses, please visit: http://www.idt.com
DAC1003D160_3 ? idt 2012. all rights reserved. product data sheet rev. 03 ? 2 july 2012 18 of 18 integrated device technology DAC1003D160 dual 10 bits dac, up to 160 mhz, 2 x interpolation 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 functional description . . . . . . . . . . . . . . . . . . . 6 8 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 thermal characteristics . . . . . . . . . . . . . . . . . . 7 10 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 7 11 application information . . . . . . . . . . . . . . . . . 12 11.1 alternative parts . . . . . . . . . . . . . . . . . . . . . . . 14 12 package outline. . . . . . . . . . . . . . . . . . . . . . . . 15 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 16 14 glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 14.1 static parameters . . . . . . . . . . . . . . . . . . . . . . 16 14.2 dynamic parameters . . . . . . . . . . . . . . . . . . . 16 15 revision history . . . . . . . . . . . . . . . . . . . . . . . 17 16 contact information . . . . . . . . . . . . . . . . . . . . 17 17 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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